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VLSI Logic Design Intern

Hewlett Packard EnterpriseChippewa Falls, WIPosted 18 hours ago

Pay
$35 – $41
per hour
Type
Internship
Full time
Where
Chippewa Falls, WI
Who
Bachelor's or Master's
Students
Apply by
Feb 26, 2027
Date from the posting

About the job

This role is designed as hybrid, with an expectation of working on average 2 days per week from an HPE office.

Who We Are

Hewlett Packard Enterprise is the global edge-to-cloud company advancing the way people live and work. We help companies connect, protect, analyze, and act on their data and applications wherever they live, from edge to cloud, so they can turn insights into outcomes quickly. Our culture values new and better ways to accelerate what's next, and varied backgrounds are valued and succeed here.

Job Description

Hewlett Packard Enterprise brings together talented people to create breakthrough technology solutions for customers. The HPE Cray Slingshot team develops the backbone technologies that move data through the fastest supercomputers in the world, which presents demanding design challenges that push the limits of modern compute.

Job Responsibilities

  • Assist with VLSI and RTL design using System Verilog.
  • Assist with creating System Verilog Assertions (SVAs) and use Formal Verification to prove design correctness.
  • Assist with writing coverage to measure stimulus quality and perform coverage analysis to identify verification holes.
  • Assist with creating scripts (Python, TCL, Perl) to improve design processes and efficiency.

Experience and Skills Required

  • Working toward a Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or an equivalent field.
  • Self-driven, with a positive, can-do attitude, and detail-oriented.
  • Experience with System Verilog for synthesis (ASIC or FPGA).
  • Proficiency in electrical engineering fundamentals, VLSI principles, digital logic, and computer architecture.
  • Strong written and verbal communication skills; fluent English.
  • Ability to work with cross-functional teams (DV, Architecture, Design, FW).

Preferred Skills

  • Understanding of the OSI model for layered networking stacks.
  • Experience with Ethernet protocols, CPU or GPU systems, and high-speed peripherals.
  • Understanding of Formal Verification and design verification using UVM.
  • Working knowledge of C/C++ or Python scripting.

What We Can Offer You

Health and Wellbeing: A comprehensive suite of benefits that supports physical, financial and emotional wellbeing.

Personal and Professional Development: Specific programs to help you reach your career goals, whether that means becoming a knowledge expert in your field or applying your skills to another division.

Unconditional Inclusion: HPE celebrates individual uniqueness and offers flexibility to manage work and personal needs.

Accessibility

HPE is committed to an inclusive and accessible workplace and encourages applications from all qualified individuals, including those with disabilities. If you need accommodation during any stage of the application or interview process, submit your request through the secure form linked here.

HPE is an Equal Employment Opportunity employer. Decisions are based on qualifications, merit, and business need. Hewlett Packard Enterprise is an EEO Protected Veteran and Individual with Disabilities. HPE will comply with all applicable laws regarding employer use of arrest and conviction records.

Skills mentioned

  • Python
  • PERL
  • TCL
  • RTL Design
  • UVM
  • Formal Verification
  • System Verilog
  • VLSI

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