Intern - DRAM Physical Design & PPA Optimization

About the Role

Join the Design Technology Co-Optimization (DTCO) team at Micron, where we work at the intersection of process technology, standard cell architecture, and design implementation to optimize power, performance, and area (PPA) for advanced memory products. We collaborate with standard cell library, RTL, and physical design engineers to evaluate design tradeoffs and develop methodologies that improve silicon outcomes.

As a DTCO Intern, you will gain hands-on experience assessing and optimizing PPA at the standard cell and logic block level. You will use industry-standard place-and-route tools and AI-enabled automation techniques to implement, benchmark, and optimize logic blocks while developing practical skills in physical design, timing closure, and design analysis.

Responsibilities

• Implement standard cell logic blocks using industry-standard physical design tools, including floorplanning, placement, clock tree synthesis (CTS), routing, and optimization activities focused on PPA assessment.
• Analyze and benchmark power, performance, and area across standard cell libraries and logic block configurations, identifying opportunities for improvement.
• Perform static timing analysis (STA), investigate setup and hold timing violations, and support timing closure activities.
• Execute physical verification checks, including DRC, LVS, and IR-drop analysis, and assist with resolving design issues.
• Leverage Generative AI, AI Assistants, and Agentic AI solutions to automate data collection, reporting, comparison, and workflow optimization for PPA analysis.

Minimum Qualifications

• Currently pursuing a B.S. or M.S. degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Demonstrated understanding of VLSI design concepts, CMOS circuits, digital logic, and the ASIC physical design flow.
• Experience through coursework, research, or projects using scripting languages such as Python, Perl, or TCL.
• Strong analytical, problem-solving, and debugging skills with attention to technical detail.
• Expected graduation date of Fall 2025 or later.

Preferred Qualifications

• Hands-on academic, research, or project experience with place-and-route tools such as Synopsys ICC2, Cadence Innovus, or equivalent tools.
• Exposure to static timing analysis tools such as PrimeTime, Tempus, or similar timing verification platforms.
• Working knowledge of design constraints (SDC), LEF/DEF formats, and physical implementation methodologies.
• Understanding of low-power design techniques and power intent standards such as UPF or CPF.
• Experience applying AI, Generative AI, Large Language Models (LLMs), or AI-Assisted coding and automation tools to improve engineering workflows and productivity.